Course / FPGA Training
Lộ trình học thực chiến: RTL → FPGA → SoC → ASIC.
Course 1: Verilog RTL Fundamentals
- Combinational/Sequential logic
- FSM design
- Testbench + simulation mindset
- Timing basics
Course 2: FPGA System on PYNQ-Z2
- Clocking, constraints (XDC)
- AXI-lite registers, custom IP
- HDMI timing + video pipeline
- Camera (OV2640) I2C init + capture
Course 3: SoC / Bus / Peripheral Design
- APB/AXI protocol
- Register map, driver concept
- LCD/IO peripherals
Course 4: ASIC Ready Flow (Overview)
- Synthesis constraints
- CDC / lint / STA mindset
- Physical awareness